My LS1021A sub block is modified from the TWR demo board and this block is going to be merged with the main FPGA board, only PCIe x4 buses connecting between them.
LS1021A TWR demo is a 8-layer board and the FPGA is a 12-layer board. The final board is going to follow the layer stack of the FPGA demo 12-layer board.
(1) impedance requirements from the LS1021A TWR demo design files. I did not find the layer stack file.
(2) FPGA board layer stack.
(3) FPGA board fabrication file.
So my question is how to recalculate the trace width and spacing numbers in the table by matching the impedance requirements with the 12-layer stack up? So that, all the high speed traces (single ended and differential pairs) would work as matched on the demo board. The layer assignments are the same as the 12-layer without using the two signal layers in the middle. Thank you!