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Undocumented Serdes Protocols for T1024

Question asked by Paulo Zaneti on Apr 17, 2017
Latest reply on May 3, 2017 by ufedor

Hi,

 

Looking at the u-boot from NXP:

 

repository: git://git.freescale.com/ppc/sdk/u-boot.git

branch: sdk-v1.9.x

file: arch/powerpc/cpu/mpc85xx/t1024_serdes.c

 

We see the following supported Serdes Protocols:

 

static u8 serdes_cfg_tbl[][4] = {
[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
[0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC1},
[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC1},
[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
};

 

But from the T1024 Reference Manual, we can not find documentation for protocols: 0x47, 0x56, 0x6F and 0x7F.

Are these protocols really valid ? Why are they not documented ?

Can we use Serdes protocol 0x47 ?

 

Thanks for your support,

Paulo Zaneti

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