I know that this MCU have 62-bit BCH Hardware ECC (Error Correction). And minimum that this specific NAND require is 60-bit ECC. Is there any other restrictions?Tnx
Micron NAND MT29E512G08CKCCB
Just adding additional information on NAND compatibility:
The NAND flash controller that is used in the i.MX7D/S in ONFI 3.2 compliant. The ONFI specification shows that the 8 bit data interface is used for command, address and data. The address is sent to the device 8 bits at a time.
In reviewing the ONFI spec, there is no number of MB listed as maximum capacity.
The i.MX7 has 1 R/B, 4 CE's, 8 bit I/O, 1 RE, 1 WE, 1 DQS, and 1 WP.
If the memory that is being selected in ONFI 3.2 compatible, then it should work with the i.MX7D part.
Hello Indir Okanovic,
I don’t have the data on the maximum NAND capacity that can be used with the i.MX7D, let me investigate. The standard has five cycle addressing so it can handle big memories.
The largest memory tested for the i.MX7D was the 32Gb Micron MT29F32G08CBADB as far as I know. But I’ve seen information on 128Gb NAND memories working on other i.MX processors so I would expect these to also be supported by the i.MX7.
I do not have the datasheet for the NAND memory you are interested but it looks fairy recent and seems to be under NDA still so I wouldn’t expect to find information on compatibility with that memory in particular.
yes unfortunately this NAND is under NDA so I cant share it.
It has 4 dies, two CE#, two R/B# and two 8bit I/O. I'm guessing that there is no limit regarding that. Also that particular memory is 512Gb and another model of this device will have 1Tb NAND so its crucial that i.MX7D can handle that.
I saw in this post NAND Flash with i.MX6Q that there is no upper limit size for i.MX6Q MCU, which is promising.
Thank you, Regards.
I confirmed that the i.MX7 NAND interface supports 27 address lines addr[0:26] and 16 data lines, but we have no information on those sizes specifically since they are fairy new.
Tnx for additional info.
Yes memory is ONFI 3.2 compatible. As I said this memory has more connections than i.MX7D but I assume they are shared connections and enable pins dictates what goes where when its used.
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