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Vybrid RD_DL_SET

Question asked by Toshishisa Sugiyama on Apr 14, 2017
Latest reply on Apr 20, 2017 by Toshishisa Sugiyama


We tested memory timing DDR validation tool.

We heard we can use fixed value for RD_DL_SET=4 and GATE_CFG=0 regardless of the result of DDR validation results.

However, the result of RD_DL_SET shows good values are 4,5,6,7. It should use 5 or 6 for RD_DL_SET. Do you recommend still use 4 regardress this results?


Best Regards,