The MCP5744P is cool, but the docs are really confusing for someone jumping into the deep end... For me, I think the biggest problem is terminology; I've been working the embedded processing scene for many years, but until now, I have only encountered Power architecture in Xilinx Virtex4. This is the background I am coming from, so please understand that I understand the concepts here, but not the terminology; this is the cause of my confusion, I am sure. To be clear, below when I "quote" something, this is to indicate where I think I am confused by terminology, or specifics of the 5744P.
I am trying to develop "exception handlers" for various issues that may arise. A partial list I was given is this:
- Critical Interrupt (IVOR0)
- Machine Check (IVOR1)
- Data Storage (IVOR2)
- Instruction Storage (IVOR3)
- Alignment (IVOR5)
- Program (IVOR6)
Here are my problems that are causing great, personal grief, that I am 1000% positive many out there can help with!
- Where the hell do I find documentation for these???
- How do I associate a handler for these? I'm not looking for the basics of how one writes an ISR or the like. I just don't know the details of how you wire one up to the "exception". For example, using other architectures, how do I set an interrupt vector to point to an ISR to service the interrupt? How is it enabled?
- In the interest of testing my handlers, how do I intentionally cause any/all of these?
To those in the know, my frustration lies in the fact that I know the information is out there, but the complexity and terminology differences between simpler (?) architectures (e.g. wicked old Intels, Coldfires, ARM) and this beast are killing my confidence!