The MCP5744P is cool, but the docs are really confusing for someone jumping into the deep end... For me, I think the biggest problem is terminology; I've been working the embedded processing scene for many years, but until now, I have only encountered Power architecture in Xilinx Virtex4. This is the background I am coming from, so please understand that I understand the concepts here, but not the terminology; this is the cause of my confusion, I am sure. To be clear, below when I "quote" something, this is to indicate where I think I am confused by terminology, or specifics of the 5744P.
I am trying to develop "exception handlers" for various issues that may arise. A partial list I was given is this:
Here are my problems that are causing great, personal grief, that I am 1000% positive many out there can help with!
To those in the know, my frustration lies in the fact that I know the information is out there, but the complexity and terminology differences between simpler (?) architectures (e.g. wicked old Intels, Coldfires, ARM) and this beast are killing my confidence!
Hello Bob,
A1: You can find the documentation in core reference manual.MPC5744P contains 2x e200z425 core,
Here is link:http://cache.nxp.com/assets/documents/data/en/reference-manuals/e200z4RM.pdf?fsrch=1&sr=2&pageNum=1
Refer to chapter 5 Interrupts and Exceptions, specially to Table 5-3. Exceptions and Conditions.
A2: I am not sure if there is a guide document for it but we have posted a lot of examples including Exception, ISR and handlers here on community:
A3:These details you can find in core reference manual in chapter 5.7 Interrupt Definitions.
Hope it helps,
Peter
Hi Peter,
I want to thank you for your kind reply. Looking back, I'm rather
embarrassed at my post; chalk it up to frustration and pre-vacation
exhaustion. I was out this last week, so I'm just getting back in stride.
Immediately before my vacation, I did talk with a colleague who, I think,
got me over the hump on this issue, at least I hope so! The problem I
think I was having is simply too much detailed information, not enough
technical overview, and a terminology mismatch. For example, I already had
the documentation resources you provided; also, I had the examples too.
(I'm not discounting you providing them, thanks!)
The problem was this: I started with this example: (
https://community.nxp.com/docs/DOC-333754). I was able to compile and run
this on our debugger/hardware, so I was encouraged. However, when I ported
it to our system, I could not get the interrupts to fire. As far as I
could determine, everything is the same between the demo code and the
ported version. This had me very frustrated, and combined with a lack of
confidence that I understood anything about the chip, caused my post.
Turns out the issue is, as expected, both unrelated to getting a Machine
Check interrupt to fire, and specific to our system. I would explain more,
but it is a long story, and I think I am past the sticking point - though I
will know more in a few hours!
Thanks again, and best regards.
Bob