Hi,
I am developing a custom board build on C291 encryption CPU. I am using 80 MHz oscillator on the SYSCLK input, since we were not able to buy 66.67 as in the reference design. The minimal ratio of CCB PLL inside the C291 is 4:1. That gives us CCB clock speed of 320 Mhz. The whole SoC and also SEC engine are running with this clock. The SoC is working fine we can run FW on the CPU, log with UART. However I found in the reference manual that maximal recomended CCB clock speed is 267 Mhz, in the section: differences among C291,C292,C293. With 80 Mhz SYSCLK it is impossible to set this clock speed. I would like to know if the SEC engine in C291 can run with the 320 Mhz. In C292 and C293 the CCB (resp. SEC) speeds can go up to 400 Mhz.
Where did the 267 Mhz reccomendation come from? Is it an output of post placement STA for the C291 chip?
Is the STA really that different between the C291 and C293? Or is the difference between the silicon dies of C291 and C293 just in placing additional block of logic (an extra SEC) and keeping the rest of the mask unchanged? Logically more logic would lead to higher fan-out and higher propagation delay and LOWER frequency...
From that I assume that the constraint of 267 Mhz for CCB in C291 is just to balance out the system, not that the logic would be unable to run on such a frequency (the communication between peripherals of SoC is working fine)...
Is there some additional logic in the C291 which is checking on the clocking? Sth what would be disabling e.g. the SEC engine or any other peripheria in C291 if CCB is set to more than 267 Mhz??
The reason why I am asking is: If the maximal frequency is truly due to some physical limits (long combinational paths or logic detecting clock over 267 Mhz) then we would need to choose 66.67 Mhz oscillator (as in reference design), which is pain in the ass, since there are very little oscillators like that on the market...
With regards
Ondrej Ille
