GbE Phy not accessible through Process(P1022) MIIM

[rammurmu]

Hi,

   I have a custom target based on P1022DS demo board. There is a SGMII PHY(Clause 22 supported) connected the processor. On trying to access the PHY registers from u-boot using mii read/write , it gives all Fs. The MAC configuration,PMUXCR and PMUXCR2 is verified and it seems OK. On using debugger after issuing a mii read command from u-boot, it could be seen in the debugger that the PHY addr(0x8) and register addr are reflected in eTSEC1 MII Management registers. However the value updated in MIIMSTAT is always 0xFFFF.

Though the internal TBI PHY (addr 0x1F) is correctly accessed from u-boot. The TBI ANA setting for the TBI PHY is also updated as per AN3869 which is 0x4001.

Please suggest what else to look into for debugging it.

Regards

Ram

[ufedor]

Please use a digital scope and check the EC_MDC and EC_MDIO signals bwhaviour when the external PHY addr(0x8) is accessed by means of the eTSEC1 MII Management registers.

If the signals pulsed, then doublecheck that the external PHY address really is 0x8.

[rammurmu]

Scope capture is OK. It has been verified for read operation for PHY addr 8 and register addr 3. PHY address is double checked. However the PHY is not responding to any register read/write(0xFFFF on read).

PHY used in BCM5461S.

In the same MIIM interface another MDC/MDIO slave is connected and this slave can be accessed correctly using the MDC/MDIO.

What else should we look for further debugging this issue ?

[ufedor]

Sorry, I do not have the BCM5461S datasheet and I can only guess whether its MII interface is capabaple to be configured to support Clause 45 instead of Clause 22.

[rammurmu]

As per DS, BCM5461S supports clause 22 , however it doesn't support clause 45.

[ufedor]

Please doublecheck the PHY connection schematics referring its datasheet.