We are using iMX6 SOC to evaluate SOC-SPI Controller to read data from high speed ADC .
We are able to do an SPI read , but the amount of time the controller takes more time ( approx 10X times more than expected )
Could you please provide pointers as to how can we remove below mentioned time delay :-
For an spi read of 18 bytes[ spi_read (spi, buf , 18)
1) SPI chip select going low to start of first SPI CLOCK = 8.27 Micro Seconds
( low_cs_to_first_spi_clock.jpg ).
2) Last SPI clock to Chip Select going high = 40.87 Micro Seconds
( last_spi_clock_cs_high.jpg )
3) No clock pulse between successive spi clock burst = 296 Micro Seconds.
( no_clock_between_two_bytes.jpg )
Attached along is the Linux DTB file and snapshot for your reference.
Could NXP members please share some pointers as to why the standard controller of iMX6 takes these extra clock pulses to perform the action.
Original Attachment has been moved to: device-tree.tar