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SPC5606S Leakage current - Sleep mode

Question asked by Anoop Aggarwal Employee on Apr 9, 2017
Latest reply on Apr 12, 2017 by Peter Vlna

This is regarding your reply on leakage / Quiescent current of the Micro SPC5606S.


As per the reference manual, it is suggested that in low power modes, the Slew Rate (SRC) bits should be de-asserted (value '0')  to avoid leakage.

0 - Pad configured as slow (default)

1 - Pad is configured as medium or fast (depending upon the pad).


After enabling slew rate control to the following Micro Pins for driving the stepper motor. To enable the slew rate feature, the Bit ‘1’ is set in the register SIUL.PCR[x].SRC.


99           M2C0M

100         M2C0P

101         M2C1M

102         M2C1P

105         M3C0M

106         M3C0P

107         M3C1M

108         M3C1P


To reduce the current leakage in STOP / low power mode, we set the Bit ‘0’ in the register position SIUL.PCR[x].SRC.

For the above register setting, the leakage current was 2.3mA (without slew rate control – Bit 0).


We performed the leakage current test again with Bit ‘1’ in the register position SIUL.PCR[x].SRC. For this setting, the leakage current was 1.4mA.


If the slew rate control (bit 0) is disabled during the low power mode, the current leakage of the Micro should come down. Here it happens in a reverse manner.


What would be the reason for this ?