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[MPC5748G] Shared RAM implementation

Question asked by Yulian Matev on Apr 4, 2017
Latest reply on Apr 10, 2017 by David Tosenovjan

Hello all,
I have two projects a "Bootloader" and an "Application".
and I would like to configure a RAM segment (128 bytes, 0x4000100--0x400017F) which is accessible
by both of them, and they can exchange data through it.


My setup:

  • Hw: Custom board
  • MCU: MPC5748G 1N81M
  • Debugger: Laurterbach Trace32
  • Compiler: GHS Multi 6.1.6


This is what I did in order to implement it:
1. Configure a "shared_ram" RAM section inside Bootloader .ld file. 

2. Configure a "shared_ramRAM section inside Application .ld file.
3. I modified startup asm code which initializes complete RAM (__ghs_ramstart -- __ghs_ramend) with 0xe800e800
so shared ram is skipped. (Note from the asm comment: This code initializes the ECC bits of the targets's SRAM by filling it with branch-to-self opcode) 

4. "shared_ram" is configured as non cache-able inside SMPU


Everything works fine when I am using the debugger,"Bootloader" and an "Application"are able to exchange data through this shared data.
The problem occurs when I run the target without debugger.
Using debug pins I am able to detect that software "crashes" the first time when a read access to the shared ram
(the one which is not initialized on purpose) is performed. Writing to this RAM is possible without an issue.


In the above sentence  "crashes" mean that software is not taking its expected path and no interrupt service routine is entered.


No special configurations for MEMU and FCCU are performed. 


Any ideas are welcome, thank you in advance!