T1040 Core Not Responding

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

T1040 Core Not Responding

Jump to solution
2,073 Views
nsutch
Contributor III

Hi,

 

We have a new design with a T1040 processor - this is the first time we have brought it up so no previous configuration existed. I've used the QCVS tool to generate the RCW and created a JTAG chain config file from the QCVS output. I've also configured a remote session to connect to the T1040 via the CodeWarrior Tap.

 

I'm getting an error (CCSProtocolPlugin : Failed to correctly configure JTAG chain). Looking at the CodeWarrior Tap console it shows ccs_error = 39.

I've also connected to the T1040 via the CCS console with the following commands:

delete all
config cc cwtap
ccs::config_chain t1040
ccs::reset_to_debug


I get the following error on the console: 'T1040: Core not responding'.

I've attached a diagram of our T1040 JTAG chain (there are no other devices on the chain). I have also confirmed that the power rails are ok and th epower manager has released the reset which feeds into the T1040's PORn signal is no asserted.

Any advice or steps to help debug the error would be much appreciated.

Thanks you

Nick

Labels (1)
0 Kudos
1 Solution
1,253 Views
nsutch
Contributor III

Adrian,

Thanks for you support with this, we have managed to connect.

For future reference, we made the following steps;

  1. Update CodeWarrior Development studio from 10.5.0 to 10.5.1
  2. Change the RCW source from 'NOR Flash' to 'I2C, SPI, QSPI, eSDHC, or hard-coded RCW' for our JTAG override RCW settings. (This is probably a no-brainer in hind-sight, as the NOR Flash is blank, but we were getting used to the tools and settings)

We were then able to connect to the probe in debug mode. Typing 'ccs::all_run_mode' into the console now shows

 

t1040: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

Thanks,

Nick

View solution in original post

0 Kudos
11 Replies
1,253 Views
addiyi
NXP Employee
NXP Employee

Try using hardcoded rcw or use the RCW override from CW. 

Adrian

0 Kudos
1,253 Views
nsutch
Contributor III

Thanks,  we are trying to override from CW. Below is the console output which shows the error 39.

ccs_open
ipaddr = 127.0.0.1
port = 41475
timeout = 60
serverh = 0
ccs_open; ccs_error = 0
ccs_get_connection_count
serverh = 0
count = 1
ccs_get_connection_count; ccs_error = 0
ccs_available_connections
serverh = 0
count = 1
ccs_available_connections; ccs_error = 0
ccs_available_connections
serverh = 0
count = 1
ccs_available_connections; ccs_error = 0
ccs_cc_version
serverh = 0
cc = 0
version.major = 0
version.minor = 0
ccs_cc_version; ccs_error = 0
ccs_set_timeout
serverh = 0
timeout = 60
ccs_set_timeout; ccs_error = 0
ccs_available_connections
serverh = 0
count = 1
ccs_available_connections; ccs_error = 0
ccs_config_server
serverh = 0
cc = 0
server_config = 0
value = 4000
ccs_config_server; ccs_error = 0
ccs_get_config_chain
serverh = 0
device_list: (size = 0)
ccs_get_config_chain; ccs_error = 0
ccs_config_chain
serverh = 0
cc = 0
device_list: (size = 1)
device[0]:: core_type=T1040(237)
ccs_config_chain; ccs_error = 0
ccs_config_template
coreh = [serverh:0;cc_index:0;chain_pos:0]
config_reg = 2
config_data = 1
ccs_config_template; ccs_error = 0
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210001
count = 1
size = 4
value: (size = 4)
0C10000D
ccs_write_register; ccs_error = 0; duration=3 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210002
count = 1
size = 4
value: (size = 4)
0D000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210003
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210004
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210005
count = 1
size = 4
value: (size = 4)
60000002
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210006
count = 1
size = 4
value: (size = 4)
00400012
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210007
count = 1
size = 4
value: (size = 4)
EC018000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210008
count = 1
size = 4
value: (size = 4)
21000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210009
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210010
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210011
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210012
count = 1
size = 4
value: (size = 4)
0002B002
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210013
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210014
count = 1
size = 4
value: (size = 4)
C5565A85
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210015
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_write_register
coreh = [serverh:0;cc_index:0;chain_pos:0]
index = 210016
count = 1
size = 4
value: (size = 4)
00000000
ccs_write_register; ccs_error = 0; duration=2 ms
ccs_reset_to_debug
serverh = 0
cc = 0
ccs_reset_to_debug; ccs_error = 39
Error message: T1040: Core not responding
ccs_get_subcore_error
serverh = 0
cc = 0
error = 5
chain_pos = 0
ccs_get_subcore_error; ccs_error = 0; duration=2 ms
ccs_reset_to_debug
serverh = 0
cc = 0
ccs_reset_to_debug; ccs_error = 39
Error message: T1040: Core not responding
ccs_get_subcore_error
serverh = 0
cc = 0
error = 5
chain_pos = 0
ccs_get_subcore_error; ccs_error = 0; duration=2 ms
ccs_reset_to_debug
serverh = 0
cc = 0
ccs_reset_to_debug; ccs_error = 39
Error message: T1040: Core not responding
ccs_get_subcore_error
serverh = 0
cc = 0
error = 5
chain_pos = 0
ccs_get_subcore_error; ccs_error = 0; duration=1 ms
ccs_close
serverh = 0
ccs_close; ccs_error = 0

0 Kudos
1,255 Views
addiyi
NXP Employee
NXP Employee
0 Kudos
1,254 Views
nsutch
Contributor III

Adrian,

Thanks for you support with this, we have managed to connect.

For future reference, we made the following steps;

  1. Update CodeWarrior Development studio from 10.5.0 to 10.5.1
  2. Change the RCW source from 'NOR Flash' to 'I2C, SPI, QSPI, eSDHC, or hard-coded RCW' for our JTAG override RCW settings. (This is probably a no-brainer in hind-sight, as the NOR Flash is blank, but we were getting used to the tools and settings)

We were then able to connect to the probe in debug mode. Typing 'ccs::all_run_mode' into the console now shows

 

t1040: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

e5500: Debug Mode

Thanks,

Nick

0 Kudos
1,255 Views
addiyi
NXP Employee
NXP Employee

Please take a look on Chapter 5.22 JTAG recommendations from AN4825, T1040 Family Design Checklist - Application Note.

Adrian

0 Kudos
1,255 Views
nsutch
Contributor III

Any help decoding ccs_error = 39 would be appreciated.

Thanks

0 Kudos
1,255 Views
nsutch
Contributor III

Adrian,

Could you confirm that, in accordance with Chapter 5.22 of AN4825, that

  • HRESET_B of the T1040 is derived from COP_SRESET_B and
  • POR_RESET_B is derived from COP_HRESET_B or the target board reset?

The reason we ask is that we have had a look at the verilog code for the FPGA on the T1040RDB evaluation card which does not appear to use COP_SRESET at all. Further,

  • HRESET_B is derived from COP_HRESET_B (albeit via some other registers and logic) and
  • PORESET_B is derived only from the target board reset signal.

The FPGA logic does not appear to match the datasheet/checklist recommendations.

Are we interpreting the diagram in Chapter 5.22 correctly and is this configuration compatible with CodeWarrior debug?

Thanks,

Nick

0 Kudos
1,255 Views
nsutch
Contributor III

Hi Adrian,

We've confirmed that we meet the recommendations in the checklist.

Thanks,

Nick

0 Kudos
1,255 Views
addiyi
NXP Employee
NXP Employee

Could you please provide the output for:

delete all
config cc cwtap
ccs::config_chain t1040

dispaly ccs::get_config_chain

ccs::all_run_mode
ccs::reset_to_debug

Adrian

0 Kudos
1,260 Views
nsutch
Contributor III

Adrian,

 

This may be relevant to the issues we are seeing...

 

We have implemented the logic circuits shown in section 4.5.1 (Legacy JTAG configuration signals) of the T1040 datasheet. Our assumption is that this is needed to operate with CodeWarrior TAP, is this correct?

0 Kudos
1,260 Views
nsutch
Contributor III

Hi Adrian,

Thanks for you support, the output is as follows:

delete all
config cc cwtap
ccs::config_chain t1040

dispaly ccs::get_config_chain

Chain Position 0: T1040

Chain Position 1: e5500 core

Chain Position 2: e5500 core

Chain Position 3: e5500 core

Chain Position 4: e5500 core

ccs::all_run_mode

t1040: Debug Mode

e5500: Execute Mode

e5500: Execute Mode

e5500: Nap Mode

e5500: Nap Mode


ccs::reset_to_debug

T1040: Core not responding

Thanks,

Nick

0 Kudos