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i.MX7D DDR3 address / command termination

Question asked by David Whitehouse on Mar 30, 2017
Latest reply on Mar 30, 2017 by Artur Petukhov


I'm looking at the i.MX7D SABRE design and the IMX7DSHDG DDR recommendations in section 3.5 - the IMX7DSHDG shows VTT termination on the address and command pins but the SABRE design has nothing. What are the rules on running unterminated? If the lengths in IMX7DSHDG Table 20 are met are the traces + rise times short enough to not worry? Some words in the IMX7DSHDG on this would be very helpful - this is very fundamental

Kind regards,