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Confirmation if it is OK to use reserved values for IFC timing registers in normal GPCM mode?

Question asked by Sina Sattari on Mar 27, 2017
Latest reply on Mar 28, 2017 by Pavel Chubakov

We have custom board designed based upon #QorIQ LS1021A ARM CPU. In the reference manual it lists the following reserved values for #IFC GPCM mode:

 

TACSE of IFC_FTIM0_CSn_GPCM =000:Reserved
TACO of IFC_FTIM1_CSn_GPCM =00000000:Reserved
TCS of IFC_FTIM0_CSn_GPCM =0000:Reserved 

 

but at the same time there is a note explaining (page 1590):

For normal GPCM mode (write transaction) all the three timing parameters (that is, TEAHC, TACSE, and TCS) should not be programmed zero together.
• For normal GPCM mode (read transaction) all the three timing parameters (that is, TEAHC, TACSE, and TACO) should not be programmed zero together.

In our setup, we have:

TEAHC =0x1 , TACSE= 0x0, and TCS = 0x0 for write

TEAHC =0x1 , TACSE= 0x0, and TACO= 0x0 for read. 

 

The system is working correctly, however I wanted to get confirmation that it is OK to use "reserved" zero settings for TACSE and TCS and TACO as long as they are not all set to zero simultaneously.

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