I'm wondering if anyone can confirm or clarify the FlexBus Clock (FB_CLK) specification on
the MCF5441x series of parts please?
In the datasheet the FB_CLK is defined as SYSCLK / 2, Sysclk being the core frequency
which is specified at min 120Mhz, Max 250Mhz. From that, I would assume that the FlexBus Clock
(being sys/2) would be min 60Mhz, Max 125Mhz, however, the spec in the data sheet states
that min = 60Mhz (as expected) but the max is [only] 100Mhz.
This leads me to wonder :
a).. Is the 100Mhz max supposed to be 125Mhz? or,
b).. Is the 100Mhz max because of a pin driver limitation (slew rate / loading etc?)
c).. if the max is actually 100Mhz, and FB_CLK is always Sys/2, then perhaps the core clock
must be limited to 200Mhz while the Flexbus is enabled?
d).. perhaps the statement that FB_CLK = SYS/2 is misleading and they are separately derived
clocks from the VCO frequency and FB_CLK must be half or less than half of the SYS clock?
I'm suspecting that the answer is 'd' but the diagrams and text are confusing, always talking about FB_CLK
being SYS/2 - for example the MCF5441x Reference Manual (Rev 4) in Table 8-4 ( PLL_DR Field Descriptions),
for OUTDIV2, and Figure 8.1 (Device Clock Connections).
Thanks in advance for any help / comments.