MKV31F512VLL12 Power On Reset not always functioning

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MKV31F512VLL12 Power On Reset not always functioning

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markwyman
Contributor III

Hi All,

I am in the midst of a prototype bring-up and development cycle of a new project, but have a real stumper holding me back. The reset of the device does not always function as expected.

At the beginning I had a 4.7K pull-up to VCC on the RESET# line, with a 10nF capacitor from reset to ground. This is to provide some low-pass filtering to remove noise that may be present when the power is ramping up, but to allow the part to come out of reset fairly quickly upon application of power. In addition there is switch to ground to allow manual reset when needed.

Bug description:

Upon first application of power, the device does not come out of POR. The oscillator wont even turn on which seems to indicate the internal clock is not even running to execute initialization code. If I press the reset button after power is applied, things run normally and it comes out of reset. I am able to program new images, single-step, and the core is at the correct frequency.

If I cycle the power and don't wait for the board to fully discharge (minutes), even cycling reset does nothing to bring the board on-line. The part remains "stuck", even though I can clearly see the reset line cycle during this time. I cannot even access the part through the debugger. I cannot recover from this without removing power, waiting quite some time, then restoring power and manually cycling reset.

I have been trying a few things:

1. Slowing the reset de-assertion by removing the 4.7K resistor, relying on the internal pull-up only. (No change)

2. Increasing the reset capacitor to 0.1uF. (No change)

3. Removing the connections to the externally sensed domains on the A/D converter core... I was hoping that these were providing leakage paths which in turn messed up the reset circuit. (No change)

4. Played around with the power-on ramp time to speed up timing from 1V/10mS to 1V/10uS to see if I wasn't coming out of power fast enough (No Change)

I have looked around the perimeter of the device for leakage paths since I am sensing some external voltage domains, but nothing over about 50mV remains after reset is asserted during a power-down. I have had a similar issue occur in the past on other vendor's processors due to even tiny leakages being enough to SCR the part, but I am not seeing that here.

What I am hoping for is some additional ideas of what to look for. 

Do I need a separate reset controller? Seems kind of silly based on what I see in the datasheet about how the reset is supposed to be handled.

I used the reference design from NXP for the oscillator, JTAG, and so on (SPF-27959_D.pdf) and started with a Design Studio project based on the board that runs fine when I get the device to reset.

Thanks for any ideas! This is entering consumer-land so it has to be reliable and inexpensive.

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markwyman
Contributor III

It is looking like these devices are hyper-sensitive to any ground bounce or power sag on any one power pin vs. another. Simply the fact I have a switching supply with large slow gulps of current is enough to force the core to SCR even though the processor is well out of the way of current flow. If I only use a linear supply, everything is OK. Use the switcher on the board, 50/50 shot of a core hang, 90% shot the reset has to be cycled to start the processor if it is not hung.

This processor is looking to be intolerant to real-world use in a noisy environment? This doesn't make any sense based on the target market of motors and high-current switching designs. Who do I contact in the US Northeast for support? Freescale used to be right next door, I could walk over for support.

I notice the reference design uses linear regulators.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mark,

I think your swich mode power supply has issue, how about using 5V swich mode power supply and use a 3.3V LDO to output 3.3V for the KV31?

BR

Xiangjun Rong

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markwyman
Contributor III

That is actually what the power structure is now:

15V Battery/Solar->4.3V High-eff switcher -> 3.3V LDO. 

What is is looking like is the switcher takes fairly large gulps of current (1.2A) and is a lower-frequency switcher (100kHz range) to increase efficiency. Right now I am investigating a new switcher running at 2MHz instead, so the regulation is tighter even though it is burst mode, and the peak currents at light loads are much smaller (160mA vs 1.2A) and full load are more reasonable.

I have my fingers crossed. I  went so far with the current design to tie all of the managed grounds together (noisy battery charger and relays on a separate ground connected via return point away from the processor), and it also made no difference.

One other thing I wonder is the high-speed process of the device, if the bypass capacitors I have chosen of X7R 0.1uF have the capability of providing the really high-speed edges the core of the processor requires. I have one on each power pin within 100mils distance with a via to the respective planes next to the bypass capacitors. However, if the device is not low-impedance at the frequencies the part is asking for, can this exasperate my issues?

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi, Mark,

I have checked our tower board schematics, the Reset circuit is a RC circuit, R is 10K ohm, the C is 0.1uF, how about using the above parameters?

If you still have issue after you change the R and C value, pls consider the regulator capability, I suppose that the 3.3V regulator or LDO can not provides enough current so that the VDD rising interim is too long. BTW, you should connect 10uF and 0.1uF for the 3.3V power supply.

The issue is not easy to fix, I am not sure if it can help you or not, pls have a try.

BR

XiangJun Rong

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markwyman
Contributor III

Unfortunately I still have the same problem.

Instrumenting the reset and VCC of 3.3V reveals timing looks excellent with reset de-asserting after power supply is in a valid range.

Pressing and holding reset during power up, then releasing, also does not allow processor to start.

What can I do now for a little design assistance with a schematic review to track the problem down?

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markwyman
Contributor III

Well,

 I finally found something that made a difference, I ran the 3.3V domain of the processor from a lab supply. With this supply, it starts and resets properly all the time. The upstream 4.3V has some bearing in how the reset functions, since I ran the input of that from the lab supply with no difference in performance, but I am not yet sure how that could be. It is a burst-mode supply for efficiency, so it is possible the bursty nature is too noisy somehow.

The layout is sound and the loop currents are well contained on the 4.3V supply, and the 4.3V domain is not tied to the processor in any way (no sense nodes, etc). There is also a very solid ground plane, in fact two of them, so unless the fabrication is bad, no ground bounce. The LDO is a very high PSRR device (>80dB) since there is also RF kicking about... 

So still confused. 

Thanks,

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markwyman
Contributor III

I have also tried this combination (10K and 0.1uF) with the same results. 

There is a switching power supply at 4.3V which is current-limited preceding a 3.3V LDO, the 3.3V is powering the processor. The LDO has a shutdown pin that has a reasonably precise voltage threshold with hysteresis. When the 4.3V supply is turning on and surpasses about 3.1V, the shutdown pin on the 3.3V LDO enables the LDO and the output for the most part "snaps" on from 0V to 3.0V in about 20uS. I can only assume this is more than fast enough to reach a valid operating voltage for the processor. The 4.3V takes 1.6mS to go from 0V to full voltage, so maybe a little slow, but the 4.3V is not on any pin of the processor, pull-up or otherwise. It is used to power a peripheral board that is not yet installed on the board so please don't consider that.

I do have two low-side shunt voltage amplifiers on the low-sides of H-bridges to detect current on two brushed DC motors, and the H-bridge and amplifier supplies are tied to my input battery supply of ~14V. I am seeing a slight output voltage from these of ~100mV that is connected to the dedicated A/D inputs of the processor whether the 3.3V is up or not. Currently that is the only thing I can think of that may be messing with the core reset functionality. I am going to lift those two parts and try again.

The interesting part is the reset timing for "removing power before reset will function" is tied to the 14V discharge rate. When the input capacity discharges below 3.0V or so (very light load on it), the processor will finally allow a reset. The 3.3V LDO and 4.3V switcher has long since discharged below 50mV before the on-board capacitance holding the 14V drops to 3.0V when power is removed (A full minute or so). Since the 14V can seemingly lock up the part for this long, it leads me to believe it is a leakage path of some sort to resolve rather than the reset pin control.

If I still get a reset problem, I will be well and truly stumped. I will be back with updates.

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