I am in the midst of a prototype bring-up and development cycle of a new project, but have a real stumper holding me back. The reset of the device does not always function as expected.
At the beginning I had a 4.7K pull-up to VCC on the RESET# line, with a 10nF capacitor from reset to ground. This is to provide some low-pass filtering to remove noise that may be present when the power is ramping up, but to allow the part to come out of reset fairly quickly upon application of power. In addition there is switch to ground to allow manual reset when needed.
Upon first application of power, the device does not come out of POR. The oscillator wont even turn on which seems to indicate the internal clock is not even running to execute initialization code. If I press the reset button after power is applied, things run normally and it comes out of reset. I am able to program new images, single-step, and the core is at the correct frequency.
If I cycle the power and don't wait for the board to fully discharge (minutes), even cycling reset does nothing to bring the board on-line. The part remains "stuck", even though I can clearly see the reset line cycle during this time. I cannot even access the part through the debugger. I cannot recover from this without removing power, waiting quite some time, then restoring power and manually cycling reset.
I have been trying a few things:
1. Slowing the reset de-assertion by removing the 4.7K resistor, relying on the internal pull-up only. (No change)
2. Increasing the reset capacitor to 0.1uF. (No change)
3. Removing the connections to the externally sensed domains on the A/D converter core... I was hoping that these were providing leakage paths which in turn messed up the reset circuit. (No change)
4. Played around with the power-on ramp time to speed up timing from 1V/10mS to 1V/10uS to see if I wasn't coming out of power fast enough (No Change)
I have looked around the perimeter of the device for leakage paths since I am sensing some external voltage domains, but nothing over about 50mV remains after reset is asserted during a power-down. I have had a similar issue occur in the past on other vendor's processors due to even tiny leakages being enough to SCR the part, but I am not seeing that here.
What I am hoping for is some additional ideas of what to look for.
Do I need a separate reset controller? Seems kind of silly based on what I see in the datasheet about how the reset is supposed to be handled.
I used the reference design from NXP for the oscillator, JTAG, and so on (SPF-27959_D.pdf) and started with a Design Studio project based on the board that runs fine when I get the device to reset.
Thanks for any ideas! This is entering consumer-land so it has to be reliable and inexpensive.