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LPC 4337 and 128Mb SDRAM

Question asked by Michael Denney on Mar 23, 2017
Latest reply on Mar 28, 2017 by Michael Denney

I am using the LPC4337 LQFP144  connecting to IS42S16800F-7  8Mx16 SDRAM chip.

I think I am setting up the EMC properly but I am not getting the results that I would expect.  Can anyone look at my setup and verify that I am not missing something.

 

void SDRAM_Init(void)
{
uint32_t pclk;
uint32_t temp;
uint64_t tmpclk;
uint32_t tmp2;

// divide core clock by 2 to get approx 102 Mhz
LPC_CREG->CREG6 |= (1 << 16);
LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG |= (1 << 5);
//LPC_SCU->EMCDELAYCLK = 0x00006666;
pclk = Chip_Clock_GetEMCRate(); 

 

LPC_EMC->STATICWAITRD0 = NS2CLK(pclk,55); // select the delay from chip select 0 to a read access
LPC_EMC->STATICCONFIG0 = 0x81; // select memory config for static chip select 0
LPC_EMC->STATICWAITOEN0 = NS2CLK(pclk,10); // selects the delay from chip select 0 or address change to output enable
LPC_EMC->STATICWAITWEN0 = NS2CLK(pclk, 10); // selects the delay from chip select 0 to write enable
LPC_EMC->STATICWAITPAG0 = NS2CLK(pclk, 55); // selects the delay for async page mote access
LPC_EMC->STATICWAITWR0 = NS2CLK(pclk, 55); // selects the delay from chip select 0 to a write access
LPC_EMC->STATICWAITTURN0 = NS2CLK(pclk, 55); // selects the number of bus turnaround cycles for chip select 0

LPC_SCU->SFSCLK[0] = (MD_PLN_FAST | SCU_MODE_FUNC5);
LPC_SCU->SFSCLK[1] = MD_PLN_FAST;
LPC_SCU->SFSCLK[2] = (MD_PLN_FAST | SCU_MODE_FUNC5);
LPC_SCU->SFSCLK[3] = MD_PLN_FAST;

LPC_EMC->CONTROL = 0x00000001;
LPC_EMC->CONFIG = 0x00000000;
LPC_EMC->DYNAMICCONFIG0 =  (1 << 10) | (1 << 7);

LPC_EMC->DYNAMICRASCAS0 = 0x00000303;
LPC_EMC->DYNAMICREADCONFIG = 0x00000003;

LPC_EMC->DYNAMICRP = NS2CLK(pclk,20);
LPC_EMC->DYNAMICRAS = NS2CLK(pclk,42);
LPC_EMC->DYNAMICSREX = NS2CLK(pclk,63);

LPC_EMC->DYNAMICAPR = 0x00000005;
LPC_EMC->DYNAMICDAL = 0x00000005;
LPC_EMC->DYNAMICWR = 2;
LPC_EMC->DYNAMICRC = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICRFC = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICXSR = NS2CLK(pclk, 63);
LPC_EMC->DYNAMICRRD = NS2CLK(pclk, 14);
LPC_EMC->DYNAMICMRD = 0x00000002;

//Delay_us(100);
Delay_ms(100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */

//Delay_us(200); /* wait 200ms */
Delay_ms(200);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */

LPC_EMC->DYNAMICREFRESH = EMC_SDRAM_REFRESH(pclk, 70); /* ( n * 16 ) -> 32 clock cycles */

//for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
Delay_ms(200); /* wait 200ms */
tmpclk = (uint64_t) 15625 * (uint64_t) pclk / 1000000000 / 16;
LPC_EMC->DYNAMICREFRESH = tmpclk; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */

LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */

temp = *((volatile uint32_t *) (SDRAM_ADDR_BASE | (3 << 4 | 3 ) << 12)); /* 8 burst, 3 CAS latency */

temp = temp;
LPC_EMC->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */

//[re]enable buffers
LPC_EMC->DYNAMICCONFIG0 = (1 << 19) | (1 << 10) | (1 << 7);

}

 

 

Test function

uint16_t data = 0x0102;
uint16_t rdData;

uint16_t *short_wr_ptr;
short_wr_ptr = (uint16_t *) SDRAM_ADDR_BASE;
uint16_t *short_rd_ptr;


short_rd_ptr = (uint16_t *) SDRAM_ADDR_BASE;

for (i=0; i<(0x01000000/2); i++)
{
   *short_wr_ptr++ = data;
   data += 0x0101;   

   rdData = *short_rd_ptr;
   if(rdData != 0x0102)
   {
      errorCount = i;

   }

}

The data seems to be getting corrupted early and and randomly.  By that I mean that within the first 14-400 writes my first address has been overwritten and it does not seem to correspond to any specific address line.

 

Any help would be greatly appreciated.

 

Thank you

Michael Denney

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