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Flex BUS interface issue.( MK66 )

Question asked by karthik A S on Mar 22, 2017
Latest reply on Mar 29, 2017 by xiangjun.rong

Hai .,


I am working with MK66FN2M0VLQ18 MCU in our customized board. I am using sdk2.0 examples for flexbus initialization.

I have configured the flexbus as 2 bytes data width , 8 WS, burst read/write disabled mode. since i am interfacing slow device I disable the auto acknowledgement (AA) and considering the RDY signal from external device. 

In burst inhibited mode if I write 32 bit data to 16 bit port size, it will generate two CS pulses and each cycle has to wait for external RDY signal to close the cycle, as mentioned in reference manual.

But in our case on getting first RDY signal , the complete bus transaction getting close irrespective of waiting for second RDY signal(hence i am getting single CS pulse despite of writing data size more then port width) .

I tried the same configuration by neglecting external RDY signal(FB_TA), in that time I am getting two CS pulse .


/**********************flex bus config routine **************************/

flexbus_config_t flexbusConfig;

flexbusConfig.waitStates = 0x0FU;
flexbusConfig.chipBaseAddress = 0x60000000U;
flexbusConfig.chipBaseAddressMask = 0x7FU;
flexbusConfig.portSize = kFLEXBUS_2Bytes;
FLEXBUS_Init(FB, &flexbusConfig);



Please suggest me If committed to any mistake while configuration.  


Thank you.,


Best Regards.,