We have a system where an FPGA and a P4080 is connected to a PCIe switch. The FPGA reads/writes from the CPU.
We recently decided to go from 128 bytes packets to 256 bytes on the PCIe and now it doesn't work anymore.
It works fine when the FPGA writes to the CPU but when is sends a Memory Read Request is casuses a FATAL ERROR in the CPU. Bit FEMR, FUF, MEFNFR and EFNFR in Root_Error_Status_Register are set.
The TLP Header sent to the CPU is 20000040'h which means Memory Read Request (4DW, no data) and 256 bytes of data.
MAX_PAYLOAD_SIZE in the switch are set to 256 bytes on both ports in the switch.
MAX_READ_SIZE in Device_Control_Register are set to "010" and MAX_PAYLOAD_SIZE in Device_Control_Register are set to "001".
Am I missing something?