Im'a facing an I2C issue wich seems to be related to I2C initialisation. Let me first describe my issue : I2C is going down, due to a RX NACK. I have to say that this issue regularly appears, but is not does not reproduce systematically.
When RX NACK is detected by firmware, I have no way to recover good I2C transaction. I need to shutdown my hardware. Then it goes fine.
I tried several value for SCL frequency in I2C controller register. Configuration seems to be correct.
Now, I tried to implement addendum A-004447 described for P1010 :
Now, I don't see RX NACK anymore, but some transcations doesn't succed due to timeout. This timeout comes from a wait for the bus to be ready before any write or read cycle.
First, I would like to know if addendum A-004447 comes from RX NACK ?
How this should be implemtend ? In I2C init, or in write/read cycle of I2C bus ?
Do you have an explanation of value used in this implementation for register (0x00, 0x22, 0xa2 and so on) ?
Why this addendum is not implemented by OS provider (Linux for example ?)
Thanks for your help
This link describes the overall addendum :