Ulrich Neumayer

MC56F8255 Flash-Clockdivider

Discussion created by Ulrich Neumayer on Mar 16, 2017
Latest reply on Apr 7, 2017 by Ulrich Neumayer

Hello,

i have a question about the MC56F8255 flash-clockdivider (register HFM_CLKD.Div[5..0]):

The user-manual

http://www.nxp.com/assets/documents/data/en/reference-manuals/MC56F825XRM.pdf

says i should avoid:

(1/Fclk - 4/Fbus) < 5us

 

In the CodeWarrior folder i can find the flash.cfg file for the MC56f8255 (5625x_flash.cfg) here:

C:\Programme\CodeWarrior_V8_3\M56800E Support\initialization\56825x_flash.cfg

In this this .cfg-file i can see the following entry:

set_hfmclkd  0x27    (0x27 = 39dez)

After Reset, MSTR_OSC = 8MHz (internal OSC aktiv), so Fclk is:

Fclk = MSTR_OSC / (hfmclkd + 1)

Fclk = 8MHz / (39 + 1) = 8MHz / 40 = 200kHz

 

After Reset Fbus is 8MHz (internal OSC aktiv).  When i'm testing the above standing rule i get the following result:

(1/Fclk - 4/Fbus)  should be >= 5us

(1/200kHz - 4/8MHz) = 4,5us

 

So the set_hfmclkd value in the init-file from the CodeWarrior-installation folder should be an illegal value. Is this correct?

 

 

The second question: Have i proberly understood that Fclk is always MSTR_OSC and not the sys_clk / 2? For Example the PLL is aktiv and the sys_clk = 60MHz, then the Fclk for flash-programming is MSTR_OSC = 8MHz and NOT 30MHz? So this were different from the flash-programming for the MC56F83xx. The MC56F83xx use for flash-programming sys_clk / 2 (30MHz in the example above).

 

Many thanks for your help!

Best regards

Ulrich Neumayer

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