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PMU Cache counters

Question asked by renato Sala on Mar 15, 2017
Latest reply on Mar 15, 2017 by ufedor

We are doing performance measurement on a LS1043A Processor using the PMU counters. We notice something that seems strange. A simple program (that runs without any operating system) contains a loop that reads from the RAM memory locations spaced of 64 bytes, all variables ( loop counter, address to read and data ) are stored in registers. The cache is enabled. As a result we have that the  L1D_CACHE_WB PMU counter has quite the same value of the MEM_ACCESS, while we expected the L1D_CACHE_WB to be quite 0 since no write-back operations should occur and, in fact the L2D_CACHE_WB is quite 0. Have you any suggestions ?