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Reference clock register setting when use ENET_REF_CLK in RGMII

Question asked by ko-hey on Mar 15, 2017
Latest reply on Mar 16, 2017 by ko-hey

Hi all

 

I want to confirm register setting when use ENET_REF_CLK in RGMII.

I'll use i.MX6Q and input 125 MHz from the external crystal to ENET_REF_CLK (V 22) for use ethernet as RGMII.

 

Could you confirm the register setting in above case ?

 

Q1.

Are the following four registers only required to be set ?
Please let me know if it is added.

 

IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK
IOMUXC_ENET_REF_CLK_SELECT_INPUT
IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL
IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK

 

Q2.

Please tell me the following settings are correct.

 

Q2-1: [IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK]

SION = 0 (Disable)
MUX_MODE = 001 (ALT1)

 

Q2-2: [IOMUXC_ENET_REF_CLK_SELECT_INPUT]

DAISY = 0 (RGMII_TX_CTL_ALT7)

 

Q2-3: [IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL]

SION = 0 (Disable)
MUX_MODE = 111 (ALT7)

 

Q2-4: [IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK]

Depends on user.

 

Ko-hey

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