Could you please to give the ddr3 configurations ?

[jason_cui]

Hi expert,

    we are doing one switch using P1022 ,and the memory is 2GB which was derived by four 4Gb ddr3.but after booting ,I got the error message like this: printf("Waiting for D_INIT timeout. Memory may not work.\n");

    Please help to check the issue

    More appreciate if ddr3 controller registers configurations are given。I will list out the datasheet about the ddr3 we are using.The yellow font in the datasheet is the kind of ddr3 we used。

    Thanks

[madhurikallem]

Did the DDR work finally?

If yes please could u share your register configurations and sysclk, ddr clk and PLL ratios?

Thanks in advance

[jason_cui]

Hi Sir,

    Thanks a lot for your reply.

    If I just use one chip select,should I config CS1_BNDS and CS1_CNFG? Or Just setting CS0_BNDS to 0x0000007f(2GB) and CS0_CNFG to 0x80014302(8 banks,15 raws and 10 lines) and leaving other configs as yours ?

    thanks

    jason

[qammarabbas]

Hi bulat‌,

There are some other registers as well like DDR_SDRAM_CFG_3 and many more. Could you please provide their configuration as well? 

[Bulat]

Following sequence is used to initialze the DDR controller in CodeWarrior. You need to update it accordance with your HW configuration (different number of memory banks/CSx, different SDRAM configuration).

    # DDR_SDRAM_CFG
    mem [CCSR 0x2110] = 0x47000008

    #CS0_BNDS
    mem [CCSR 0x2000] = 0x0000003f

    #CS1_BNDS
    mem [CCSR 0x2008] = 0x0040007f

    #CS0_CNFG
    mem [CCSR 0x2080] = 0x80014202

    #CS1_CNFG
    mem [CCSR 0x2084] = 0x80014202

    # TIMING_CFG_0
    mem [CCSR 0x2104] = 0x00330104

    # TIMING_CFG_1
    mem [CCSR 0x2108] = 0x5c5bd746

    # TIMING_CFG_2
    mem [CCSR 0x210c]= 0x0fa8d4ca

    # TIMING_CFG_3
    mem [CCSR 0x2100] = 0x00010000

    # DDR_SDRAM_CFG_2
    mem [CCSR 0x2114] = 0x24401051

    # DDR_SDRAM_MODE
    mem [CCSR 0x2118] = 0x00421221

    # DDR_SDRAM_MODE_2
    mem [CCSR 0x211c] = 0x04000000

    # DDR_SDRAM_MD_CNTL
    mem [CCSR 0x2120] = 0x00000000

    # DDR_SDRAM_INTERVAL
    mem [CCSR 0x2124] = 0x0a280100

    # DDR_DATA_INIT
    mem [CCSR 0x2128] = 0xdeadbeef    
    
    # DDR_SDRAM_CLK_CNTL
    mem [CCSR 0x2130] = 0x02800000    

    # TIMING_CFG_4
    mem [CCSR 0x2160] = 0x00220001

    # TIMING_CFG_5
    mem [CCSR 0x2164] = 0x02401400

    # DDR_ZQ_CNTL
    mem [CCSR 0x2170] = 0x89080600

    # DDR_WRLVL_CNTL
    mem [CCSR 0x2174] = 0x8655a608

    # DDR_CDR_1
    mem [CCSR 0x2b28] = 0x00000000
    
    # DDR_CDR_2
    mem [CCSR 0x2b2c] = 0x00000000

    #delay before enable
    wait 500

    # DDR_SDRAM_CFG
    mem [CCSR 0x2110] = 0xc7000008
    
    #wait for DRAM data initialization
    wait 2000

Regards,

Bulat