Memory mapping on MC9S12DG128

[condor]

HI, everyone.

I'm working with Freescale uCs only a few days and I have some problems with understanding of memory mapping.
I'll try to describe my problems:
1) this uC has 8k RAM and in user guide written that this memory can be mapped to any 8k boundary. But INITRM register defines the upper 5 bits of RAM address. So RAM can be mapped to any 2k boundary.
2) After reset RAM memory mapped to 0x0000-0x1FFF. But the INITRM reset value is 0x09 (hex). So RAM should be mapped to 0x0800-0x2800.

Can you explain me this contradictions?
Thanks.

[kef]

1) 8k RAM can't be mapped to any 2k boundary. Irrelevant INITRM bits (bit4 to bit0) are ignored. So 8k RAM can be mapped to any 8k boundary, only 0-1FFF, 2000-3FFF, 4000-5FFF and so on.

2) By default 8k RAM is mapped to 0-1FFF. By default registers block is mapped to 0-3FF. Registers block takes precedence over flash, EEPROM and RAM, so by default only 7k out of 8k RAM are accessible at 400-1FFF.

[condor]

Thanks for the answer:
1) Can you give me the link to the document where 4-0 bits are ignored? In User guide INITRM is defined like this:
bit7 - RAM15
bit6 - RAM14
bit5 - RAM13
bit4 - RAM12
bit3 - RAM11
bit2 - ignored
bit1 - ignored
bit0 - RAMHAL

So only 2-0 bits are ignored in address and therefore boundary is 2k. Is this a mistake in user guide?

2) The INITRM reset value is 0x09, so bit3 is 1 and base RAM address should be 0x0800. If bit4 and bit3 are really ignored then everything is ok and the base address 0x0000.

[CompilerGuru]

The RAMHAL is not ignored,
I searched for RAMHAL in this forum and found
http://forums.freescale.com/freescale/board/message?board.id=16BITCOMM&message.id=976

which also contains a reference to this:

http://www.freescale.com/files/microcontrollers/doc/eng_bulletin/EB386.pdf?srch=1

which also mentions in which cases the lower bits of INITRM are ignored.

hope it helps :smileyhappy:


Daniel

[condor]

Thanks!
Now everything is clear.