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IMX6: Clocks Alignment of LVDS Output in Split Mode

Question asked by Denis Alain on Mar 14, 2017
Latest reply on Aug 31, 2017 by Ankit Patel


I look at the datasheet and inside the PRM of the IMX6: no luck! I would like to know if both LVDS clocks of both ports will be aligned in split mode? Or do I need to deal with some shift inside my FPGA? In other words, can I use only the clock of port0 for both LVDS ports?


Denis Alain, Eng.