How does the DMA asynchronous wake up work?
It takes a bit longer than i expected but im not sure ive got the full picture.
e.g. below i have guessed that section 4+5 is the bus clock booting up, then 6+7 is the DMA getting ready, why does it take 4.3~4us at 48MHz? (equivalent of >200 cycles).
Does it have to wake up the flash through the flash controller (i.e. it doesn't know if it might have to access flash?)
and if so, can it be configured to let it know it wont access flash, so it starts up quicker?
Im using K22 freedom board. i have code working where the ADC wakes up the DMA (from VLPS mode) to move the result. the DMA is using the bus clock at 48MHz or 4MHz. The DMA is dominating the time/energy.
from attached picture (green trace is current monitor on Vdd), i have verified 1 and 2 are adc sampling and processing, but not sure my explanation below for the rest of the sections are correct?
(There is no other isr/wakeup except the dma loop complete (every 512 times). the scope is triggered from the current trace and heavily averaged, so this is negligible) . the blue trace shows the ADC pin at 2mV/div ac coupled.
section 8 is around 1.2us for bus=48MHz, and 9~11us for bus=4MHz
1 ADC Sampling
2 ADC Converting
3 ADC Processing
4 Bus clock booting up from datasheet: IRC48 takes 2-3us to start. Pulse current starting up flash?
5 " " "
6 DMA booting up
7 " " "
8 DMA complete actions This section is roughly the actual DMA active time
9 " " " 9 and 10 are time constants of the circuit. To be used
10 " " " for integrating current, but not for estimate of DMA time
if anyone has an idea of alternatives for these sections it would be very helpful.