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LS1020E - IFC Addressing Mode 1

Question asked by Dusan Ferbas on Mar 9, 2017
Latest reply on May 18, 2017 by Dusan Ferbas

I started a new thread as requested by Alexander at Query on cfg_rcw_src[6:7] in RCW Source Encoding.

Question is how to connect 16 bit NOR flash memory to the LS1020 in ADM mode 1?

 

Maybe I am a big endian guy for a long time, but anyhow.

In the reference manual (LS1021ARM.pdf), chapter 23.4.1.2.2 Mode 1 pin muxing, figure 23-16, there is a description, how internal address is shifted to be divided into AD and ADDR buses. Also for 16 bit access only even addresses make sense, thus the lsb is shifted out. As far as clear, but why do we need bit reverse? The figure 23-16 shows bit to bit wiring, AD0 to AD0 on memory or probably a discrete solution with a latch. On the contrary, figure 23-16 shows address bit 30 going to signal AD0. Can someone explain this?

 

"Right shift the swapped address by ADM_SHFT programmed to align msb to index 31 (in same line as in left shift mode)". Why the msb is marked as 4? Does it mean the address is hold in address register in big endian order?

 

Now, where the realpoint is: if we come to booting, change to rcw_src is required. We can select ADM shift of 4, which is probably for 8 bit memories. Will this rcw_src setup work with 16 bit memories? I think yes, but as they did not, I would like to eliminate this problem.

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