DRAM Calibration using DDR Stress Test Tool V2.60

[kishorr]

I am working DDR calibration using NXP DDR Test tool. We have imx6qp based custom hardware.

I am following the below procedure

1. Run NXP DDR test tool to get the calibrated values for the MMDC registers (12 registers)

2. Run the Calibration test multiple times and capture the results.

3. Based on the values in the multiple iterations, take the values which are mostly repeated

4. Update the script with the selected values

5. Run the DDR test tool, load the updated script and execute the stress test instead of calibration test

Most of the times the stress test fails and very few time it succeeds.

The overnight test fails all the times. 

I would like to know what is the best way to get the calibrated values.

If it is difficult to get optimised values for a single board, is it possible to get the optimisedregister values which run across the boards.

Appreciate any useful information that will help me to completed this process.

Below capture logs in fail and pass cases.

Thanks

Kishor

Failure case:

DDR Stress Test Iteration 1
Current Temperature: 40
============================================

DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
test1 Address: 0x18695440
Data initally read was: 0x55555555
Data re-read is: 0x55555555
But pattern was: 0x5e5f95f8
Bit location: 0x0b0ac0ad
Error: failed to run stress test!!!

Success case:

DDR Stress Test Iteration 1
Current Temperature: 42
============================================

DDR Freq: 528 MHz
t0.1: data is addr test
t0: memcpy10 SSN x64 test
t1: memcpy8 SSN x64 test
t2: byte-wise SSN x64 test
t3: memcpy11 random pattern test
t4: IRAM_to_DDRv2 test
t5: IRAM_to_DDRv1 test
t6: read noise walking ones and zeros test

Success: DDR Stress test completed!!!

[Yuri]

Hello,

  Perhaps the problem relates to some inaccuracy  in memory PCB design.

You may look at sections 3.3.1 (Identifying Issue on Calibrations) and
3.3.2 (Identifying Issue on Stress Test) of the following document.

Freescale i.MX6 DRAM Port Application Guide-DDR3 

Please check Your PCB design  using Chapter 3 (i.MX 6 Series Layout Recommendations)
of the  Hardware Development Guide

http://cache.nxp.com/assets/documents/data/en/user-guides/IMX6DQ6SDLHDG.pdf 

  In particular, please use Excel page named “MX6 DRAM Bus Length Check” in “HW Design

Checking List  for i.Mx6”, linked below.
 
https://community.nxp.com/docs/DOC-93819  

  Also, You may  verify Your design, using the recent design checklist, that may be found

in the HW_Design_Checking_List

Have a great day,
Yuri

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[kishorr]

Thank you very much Yuri. The PCB design looks to be as per the recommendations.

Also on our current hardware, we are using the part  MT41K1G16 (2Gbyte) 

Total 4 parts are used which should provide 8Gbytes of memory, but as CS0 is only used total accessible memory is 4Gbytes. CS1 not connected.

I have attached NXP excel sheet that we using to create the DDR script file. I was thinking if anything is wrong with the configuration provided in the excel sheet. I am attaching it. In case you find any issues please let me know.

Device Information
Manufacturer:	Micron
Memory part number:	MT41K1G16
Memory type:	DDR3-1600
DRAM density (Gb)	8
DRAM Bus Width	16
Number of Banks	8
Number of ROW Addresses	16
Number of COLUMN Addresses	10
Page Size (K)	2
Self-Refresh Temperature (SRT)	Normal
tRCD=tRP=CL (ns)	21
tRC Min (ns)	21
tRAS Min (ns)	62.5
System Information
i.Mx Part	i.Mx6Q
Bus Width	64
Density per chip select (Gb)	32
Number of Chip Selects used	1
Total DRAM Density (Gb)	32
DRAM Clock Freq (MHz)	528
DRAM Clock Cycle Time (ns)	1.894
Address Mirror (for CS1)	Disable
SI Configuration
DRAM DSE Setting - DQ/DQM (ohm)	40
DRAM DSE Setting - ADDR/CMD/CTL (ohm)	40
DRAM DSE Setting - CK (ohm)	40
DRAM DSE Setting - DQS (ohm)	40
System ODT Setting (ohm)	60

Thanks

Kishor

[Yuri]

Hello,

  Please create request Sales and Support|NXP 

and send DDR schematic (connections between i.MX6 and MT41K1G16).

Regards,

Yuri.