P1011 DDR3 clock centering validation fails with D_INIT. Some cells pass, some fail. We turn EEC on and we get more failures. Should we leave ECC off to run this test. Also READ ODT and WRITE ODT all fail with D_INIT when we use the WRLVL and CLK adjust settings when ECC was on. If we use the clock centering values we obtained with ECC off READ ODT and WRITE ODT passes some values. Signal integrity looks good.