Let me ask UPOSC bit.
S12 uC uses external resonator, and the manual mentions "UPOSC becomes 1 once external resonator clock becomes stable (not locked)".
I'd like to know how to check if external clock is stable or.
Would you please let me know?
If an external oscillator is not used (OSCE bit is 0, then UPOSC stays 0), in this case, use the LOCK bit to verify the bus clock is working within the expected tolerance.
When the external oscillator is used (OSCE=1) and the oscillator is qualified then LOCK and UPOSC are set. Loosing PLL lock status (LOCK=0) means that the oscillator status information (UPOSC=0) is cleared as well. You can use Oscillator status interrupt (OSCIE) which is triggered when UPOSC changes.
System clocks can be derived directly from OSCCLK only if UPOSC=1. If UPOSC is cleared, PLLSEL is set automatically and the Bus clock source is switched back to the PLL clock.
If the clock monitor is enabled, it will reset the MCU in the case of a crystal oscillation stop occurs.
Retrieving data ...