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FRDM-KL03Z: Need help with interrupts in TPM module!

Question asked by Sara Stout-Grandy on Mar 2, 2017
Latest reply on Mar 3, 2017 by Mark Butcher

Hello,

 

I have the following code set-up to trigger an interrupt when the timer on channel 0 overflows. I have written an interrupt handler, but the various items in the routine are not being implemented. Also, when I try to reset the interrupt flags by writing a "1" to the appropriate registers, they appear to stay set and not get cleared. My code is below.

 

I'm also confused by the LED color since LED3 is supposed to be blue but I see green.

 

Thanks!

 

#include <stdio.h>
#include <string.h>

 

// SDK Included Files
#include "fsl_tpm_driver.h"
#include "board.h"
#include "fsl_debug_console.h"
#include "fsl_interrupt_manager.h"

 


//Code to use the TPM interrupt

 

int main(void)
{

 

    uint16_t uMod, uCnV;
    uint32_t freq, instance, clockps,port;
    uint8_t channel, value;

 

    hardware_init();
    instance=BOARD_TPM_INSTANCE;
    channel= BOARD_TPM_CHANNEL;

 

    CLOCK_SYS_EnableTpmClock(instance);

 

    TPM_Type *tpmbase=g_tpmBase[instance];

 

    //Set Port (Ports are already set in the pins_mux.c file)
   // PORT_WR_PCR_MUX(PORTB, 11, 010); //Set the Alt2 muxing on Port B, pin 11
   // GPIO_WR_PCOR(gpioBase, 0u);//Clear the output port
    //GPIO_WR_PDDR(portBase, 1u); //Set Port as output

 

    //Set up the Timer
    TPM_BWR_SC_PS(tpmbase, 1u); //Set the prescaler value to divide by 2
    TPM_BWR_SC_CMOD(tpmbase, 00); //Disable the counter until the MOD is set
    TPM_BWR_SC_CPWMS(tpmbase, 0u); //Set the counting mode to up only
    TPM_BWR_CNT_COUNT(tpmbase,35u); //Set the count value, writing any value clears the register

 

    clockps=(1<<TPM_BRD_SC_PS(tpmbase));
    freq=CLOCK_SYS_GetTpmFreq(instance)/clockps; //System clock=48MHz
    //uMod=freq / 120000u -1;
    uMod=50;
    TPM_BWR_MOD_MOD(tpmbase, uMod); //Sets the TPM peripheral timer modulo value

 

    //Setting up for Toggle output on Match on CS0SC
    //value=0x14u; //00010100 binary for Toggle Output on match where order of bits is: CHF CHIE MSB MSA ELSB ELSA 0 0
    value=0x28u; //00101000 binary for Edge-Aligned PWM where order of bits is: CHF CHIE MSB MSA ELSB ELSA 0 0
    TPM_WR_CnSC(tpmbase,0,value); //The CnSC register needs to be written all at once!

 

    //Set the Timer Channel Count Value for PWM
    uCnV=uMod * 50/100; //sets the count value to be the PWM duty cycle...x/100 is the duty cycle
    TPM_BWR_CnV_VAL(tpmbase, channel, uCnV); //Sets the TPM peripheral timer channel counter value

 

    //Set the Configuration registers
    TPM_BWR_CONF_TRGSEL(tpmbase, 1000);//Trigger Select for TPM0 overflow
    TPM_BWR_CONF_CROT(tpmbase, 0); //Counter reload on trigger rising edge, 1=enabled
    TPM_BWR_CONF_CSOO(tpmbase,0); //Counter stop on overflow, 1=enabled
    TPM_BWR_CONF_CSOT(tpmbase, 0); //Counter start immediately once enabled
    TPM_BWR_CONF_GTBEEN(tpmbase, 0); //Global time base enable, 0=all channels use internal TPM counter as timebase
    TPM_BWR_CONF_DBGMODE(tpmbase, 00); //Debug mode, set to have counter continue working in debug mode

 


    TPM_BWR_CnSC_CHIE(tpmbase,0,1); //Enable interrupts
    TPM_BWR_SC_TOIE(tpmbase, 1); //Enable the Timer overflow interrupt
    TPM_BWR_SC_TOF(tpmbase, 1);//Clear the TOF field (timer overflow)
    TPM_BWR_SC_CMOD(tpmbase, 01); //Start the counter. Set the TPM counter clock mode to increment on every TPM counter clock

 

    //Interrupt stuff
    NVIC_ClearPendingIRQ(g_tpmIrqId[instance]);
    //INT_SYS_InstallHandler ( TPM0_IRQn, *TPM0_IRQHandler );
    INT_SYS_EnableIRQ(TPM0_IRQn);
   // INT_SYS_EnableIRQGlobal;

 

    while(1){}
}

 

void TPM0_IRQHandler(void)
{
    TPM_Type *tpmbase=g_tpmBase[BOARD_TPM_INSTANCE];
    LED3_EN;
    LED3_ON;
    LED3_OFF;
    LED3_DIS;
    PRINTF("\r\nRunning the SaraTMRINT project: This is the interrupt\r\n");

 

    TPM_WR_STATUS(tpmbase, 1); //Clear the entire interrupt flags

 

}

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