We are developing a 6sl based board that uses a xilinx spartan6 fpga. On our board, the fpga is handling power and resets. It is the fpga that releases the 6sl from reset. The fpga also controls all of the interface pins that are used as the BOOT_CFG pins. Because of this, it looks like the buffer based bootstrapping used on the 6sl evk reference design is unnecessary for our board. Our boot sequence will be like the following:
- power is turned on
- fpga turns on
- fpga enables regulators that power the PFUZE100 system pmic
- fpga sets the BOOT_CFG pins to appropriate values
- fpga releases 6sl from reset
- bootrom reads BOOT_CFG pins
- bootup proceeds
- using time delay, fpga switches BOOT_CFG pins to its intended purpose
- 6sl switches the pinmux for the relevant BOOT_CFG pins to its intended purpose
This eliminates the need for the 74244 buffer and 74125 as well as the bootstrapping pullups/pulldowns because we can then change the BOOT_CFG values using FPGA bitfile.
My question is therefore related to why there are 4.7kOhm resistors on the output of the buffers that feed to each BOOT_CFGx[x] pin. I'm referring to the 4.7kOhm like R321 (screenshot attached from 6sl evk reference design) on the output and not the pullup or pulldown. I'd like to understand what its purpose is so that we can decide whether we need it when we are controlling that pin directly with an fpga on our board.