S12ZVMB: P0, P1, E0, E1 usage as i/o

[rajivbandodkar]

Hi,

Refer to datasheet selection. Here can all 4 pins HS1, HS2 and PP0, PP1 be used independantly as IO. I have tried but not working. Am I missing any other setting for making all the four pins at independent IOs. I have similar issue with PE0 and PE1.

[rajivbandodkar]

Hi Daniel,

Can you try on the S12ZVMB EVM and check if ti is working with a very simple code. 

Regards,

Rajiv.

[danielmartynek]

Hi Rajiv,

I would like to but we don't have the S12ZVMB EVM board.

Regards

Daniel

[danielmartynek]

Hi

Do you mean independent drivers and GPIO?

HS0-1 pins are set as independent drivers after reset (Tab 2-8), HSCR[HSEx] enable the drivers and HSDR[HSDRx] are used to control the drives. If PWM or TIM1 module is enabled and these pins are routed to the module in MODRR4 or MODRR5, the module takes control over these pins. That applies in general for all modules and associated pins (Table 2-45).

Note, registers MODRR4 and MODRR5 can be written only once in normal mode.

Port E and P are set as GPIO after reset (tab 2-3, 2-6). However, if external oscillator is enabled CPMUOSC [OSCE] the PE0 and PE1 pins are exclusively reserved for the oscillator and they cannot be used anymore as GPIO.

Regards

Daniel