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Question asked by Ilario Gottardello on Feb 28, 2017
Latest reply on Mar 10, 2017 by Ilario Gottardello
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Good morning to all,


I need to clarify a bit the power rails associated with the network section of i.MX6 quad.


We are developing a SoM that will be used on various products. Devices well be mounted on the base boards, so we need to export all the functions on the connector. Now, what we are trying to achieve with the LAN section is to have a design flexible enough to allow RMII PHY or RGMII PHY based on needs.


Basic assumptions are:

GPIO16 is already used for other things so it's not considered here

Clock is sourced from the PHY, because we already have daughter boards that only provide it

GPIO of our boards are all 3V3, so we really need to remain compatible, the only exception could be the gigabit PHY


Now, if I get it right from Reference Manual, RMII signals are under NVCC_ENET power domain, and RGMII signals are under NVCC_RGMII power domain. But, two of them are inverted: RGMII_TX_CTL pad (C23), which is used by RMII to source the clock, is under NVCC_RGMII power domain, and ENET_REF_CLK pad (V22), which is used by RGMII to source the clock, is under NVCC_ENET.


First question: did I get it right? Are they really inverted like this?

Second question: Why did you make it like this? It doesn't make sense to me.

Third Question: Does this mean that, if we want to make them interchangeable, we must connect the two power rails toghether or use level shifter on the base board? Are there any solutions that well permit us to maintain 3V3 for RMII?


Thank you very much

Have a nice day