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Regarding POR settings of P1013

Question asked by rinku takkar on Feb 28, 2017
Latest reply on Mar 7, 2017 by rinku takkar

We are driving the POR signals of P1013 from lattice cpld LCMXO2-1200UHC as follows : -


cfg_sys_pll <= "011";
cfg_ddr_pll <= "010";
cfg_core0_pll <= "100";

cfg_core1_pll <= "100";
cfg_rom_loc <= "1110";
cfg_serdes_ports <= "10111";
cfg_ddr_speed <= '0';
cfg_srds2_refclk <= '0';
cfg_elbc_ecc  <= '0';
cfg_tsec1_port <= '1';
cfg_tsec2_port <= '0';
cfg_plat_speed <= '1';
cfg_core0_speed <= '1';

We have asserted the hreset signal for around 125 us and maintained a set up time of 100 us and hold time of 2 sysclk cycles(30 ns) for POR signals with respect to deassertion of hreset signal. PFA the simulation snapshot for the same,



Processor is being detected using lauterbach debugger cable but in target reset fails and when we try to read the bootstrap configuration it shows bus error. Following commands have been used for the same:-


system.detect cpu

system.memaccess cpu

system.mode attach

per , "global utility tool , power-on" /dualport


We have also probed the asleep signal . It is being driven high and then negated. As per the reference manual (pg148)  this happens when the processor properly initializes after a POR sequence.


So we are confused whether the POR setting is wrong or the timing is incorrect or any other issue. Kindly guide.