We are using an iMX7 Dual SoC, and while we appreciate the inclusion of a PCIe interface we currently have no use for it in our design. In Section 3.2 of the datasheet (iMX7Dual Family of Applications Processors Datasheet, Rev. 2, 06/2016), Table 5 recommends that if not using PCIe to leave a number of signals floating, and to tie PCIE_VP, PCIE_VP_RX, PCIE_VP_TX, PCIE_VPH, PCIE_VPH_RX, PCIE_VPH_TX, and PCIE_REXT to ground.
In Table 8 of the hardware development guide (Hardware Development Guide for i.MX7Dual and 7Solo Applications Processors, Rev. 0, 07/2016), note 5 says that if JTAG boundary scan is to be supported, the following supplies must be powered: PCIE_VP, PCIE_VPH, PCIE_VP_TX (the doc has a typo on that last signal name).
The question is, in the case of not using PCIe, but desiring to support boundary scan, exactly what should all the other pins be connected to ?
The literal interpretation of the documentation results in:
PCIE_VP powered by LDO_1P0D
PCIE_VP_RX tied to ground
PCIE_VP_TX powered by LDO_1P0D
PCIE_VPH powered by VDDA_PHY_1P8
PCIE_VPH_RX tied to ground
PCIE_VPH_TX tied to ground
PCIE_REXT tied to ground
Is this correct ?
I'm assuming that since PCIE_VP, PCIE_VPH, and PCI_VP_TX are only used for infrequent JTAG, it is OK to only provide the internal LDO_1P0D regulator with minimal bypassing (0.22uF), and supply the PCIE_VPH supply from the +1.8V switch (VDDA_PHY_1P8) without bypassing. MIDI is also powered down via the instructions in Table 5 of the datasheet. Comments ?