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MM912J637 D2DFCLK and PRESC register

Question asked by Ian Wilson on Feb 27, 2017
Latest reply on Mar 6, 2017 by Tomas Vaverka

Hi all,

We are using the MM912J637.  Have been for a few years now but I think we are uncovering an old issue now.


I am finding the lifetime counter is giving a wake-up about 5% too early. I want 5 seconds but am seeing about 4.75 seconds.  The error should be better than this as the system has been running and so the ALFCLK should have a recent sync against D2DSCLK. D2DSCLK should have an accuracy better than ~1%. (I'll ask another question on this though.)


In working through this I am looking at the datasheet for the D2DFCLK and D2DSCLK settings.  The description for the use of PRESC is:

Q1: Is the denominator for D2DFCLK really "2x(PRESC[15,10]+PRESC[9])"? So are there really two ways to get a denominator of 22, say; one with PRESC[15,10]=11 and PRESC[9]=0, and the other with PRESC[15,10]=10 and PRESC[9]=1? This seems a rather unusual implementation? Is the final parenthesis in the correct location?

Q2: As written, Eqn. 2 can't have an odd denominator.  Is this really the case?


Further down in the datasheet (in section of version V5.0 Jan 2015 of the datasheet), Table 69 has Recommended Clock Settings.  The right-most column looks like:

Q3: What is the "63:64" content showing?  Why the semi-colon?

(Also note that the register here is shown as PRESC[15:9] - using a colon rather than a comma as before (minor issue) but now showing bits 15 down to 9 - so a bit inconsistent.)


Many thanks for any assistance anyone can give.