i am looking at the timing of ADC conversions. i have an issue where it roughly corresponds with expected times. with the debugger connected, but becomes longer with the debugger disconnected. (constant extra 7.5us for any mode). Im using a segger jlink, power cycled after removing.
attached graphs -
Using the FRDM-K22 board (MK22FN512VLH12). The ADC is triggered by hardware (LPTMR). long sampling is disabled. high speed is off, hardware averaging is off. set to single ended 12b (20 cycles conv.). The clock is the ADACK (div 1).
then i looked at the times for low power on/off, and clock enabled or not ('autowake' the module wakes the clock up when it needs to for a conversion, as i understand).
blue line is a x10 probe connected to the ADC input channel with no other load. it is AC coupled and 1mV/div scale.
light blue - goes high on first line after waking up from sleep, when the ADC complete IRQ triggers.
The times for 'auto wake' and 'clock always on' are the same, i cant observe anything that shows the ADACK clock waking up in 'autowake' mode.
- The large shifts must be to do with switching the sampling capacitor in/out on the channel, but struggling to get my head around why this happens more than once? i.e. maybe expect one shift up when connecting, then one shift down when disconnecting.
- and why there is a difference without the debugger (especially figure 6 and 8).
- Zooming in on the pulses (coupling - two pulse per clock (rising and falling edge)) shows that they correspond to 2.54MHz and 5.21MHz in low power and normal clock mode - confirming the datasheet typical values for the internal ADC CLK.
Im not sure if im missing something obvious about the debugger? but even still, without it the timings are longer than expected: