SPI/QSPI/I2C LS1043ARDB transfer size, packet fixed size, # of bits transferred?

[tracysmith]

What is the single size of a single transfer over spi compared to i2c.  Are the packets a fixed size?  If yes, then how many bits are transferred? 

Also, is it one packet burst for every time the CSn goes low or can we have multiple bursts of size X when the CSn is asserted?

Also, I see on page 62 of LS1043A.pdf that there’s a mention of SPI and QSPI?  Are they separate functions or the same?

[r8070z]

Have a great day,

The I2C data transfer granularity is 8 bits. The SPI data transfer granularity is programmable. Minimal is 4 bits maximal is 32 bits. Let call it character. The I2C and SPI protocol do not specify maximal transaction size. The LS1043A I2C and SPI controllers can transfer arbitrary number of characters. Both have special stop conditions at data transfer end.
Some SPI peripherals must be deselected between every character. Other peripherals must remain selected between several sequential character transfers. The LS1043 SPI controller can support both types.
The LS1043A has separate SPI controller and QSPI controller.

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