Hi Jeremiah,
The Individual masking is enabled by MCR[IRMQ] bit. Once set the individual RX masking is enabled. The ID Filter elements then use RX individual mask registers and RX FIFO global mask register as per setting of CTRL2[RFFN]
For your setting above highlighted option is valid.
The FLEXCAN_DRV_SetRxMaskType (FSL_CANCOM1, 1) is used to set the MCR[IRMQ] bit. Must be written in Freeze mode.
Regarding the data bytes swapping; the module itself does not do any byte swapping.
Seems the API does this. Not sure why. See more in functions FLEXCAN_HAL_ReadRxFifo() and FLEXCAN_HAL_GetMsgBuff(). But it looks the bytes are swapped when regular MB is read, not the RX FIFO.
Your code for clearing the RXFIFO could work.
You can also use CAN_IFLAG1[BUF0I] to empty FIFO content as written in chapter 47.5.8.2 "Clear FIFO Operation" of the RM. Writing 1 to CAN_IFLAG1[BUF0I] will empty the RXFIFO, but must be done in Freeze mode. The code could be following…
FLEXCAN_HAL_EnterFreezeMode(FSL_CANCOM1); // set Freeze mode
FLEXCAN_HAL_ClearMsgBuffIntStatusFlag(FSL_CANCOM1, 0xE1) // empty fifo and clear other RXFIFO flags
FLEXCAN_HAL_ExitFreezeMode(FSL_CANCOM1); // exit Freeze mode
BR, Petr
Jeremiah,
I believe you are correct I ran into the same thing. I am using the kinetis K20DX256 (KSDK 1.3) and when we call FlexCanDevice_SetRxIndividualMask() in the driver it calls FLEXCAN_HAL_SetRxIndividualExtMask() which writes to the CANx_RXIMRn register:
FLEXCAN_HAL_SetRxIndividualExtMask(){
....
CAN_WR_RXIMR(base, msgBuffIdx, CAN_ID_EXT(extMask));
....
}
CAN_ID_EXT is defined as:
#define CAN_ID_EXT_MASK 0x3FFFFu
#define CAN_ID_EXT_SHIFT 0
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
There are two issues with this:
1. CAN_ID_EXT_MASK would only set the extended ID part of the ID even though the maximum possible value of an extended mask would be 0x1fffffff
2. If RX is set up to use a FIFO then we need to look at RXFGMASK register to see what the bits mean. In the CANx_RXFGMASK definition, if we have selected to use full RXIDA format then the ID would be bits FGM[29:1]. So therefore we would need to shift by 1 bit (as you have done)
This is the solution I had for this issue. I modified the driver so
FLEXCAN_HAL_SetRxIndividualStdMask{
...
CAN_WR_RXIMR(base, msgBuffIdx, ((CAN_ID_STD(stdMask))<<1));
..
}
FLEXCAN_HAL_SetRxIndividualExtMask(
...
//The reason the value has been OR'ed by 0x40000000 is because we want to set the IDE bit since it is an extended message
CAN_WR_RXIMR(base, msgBuffIdx, (((extMask & 0x1FFFFFFF)<<1))| 0x40000000);
...
}
Note: This solution works for FIFO masks but will not work for mailboxes because CANx_RXMGMASK is defined as MG[28:0]
Thanks,
Abid.
