AnsweredAssumed Answered

ADC clock below 2.0MHz limit

Question asked by Alexander Farley on Feb 23, 2017
Latest reply on Mar 2, 2017 by Alexander Farley

I'm getting  a compiler warning after adding 2 ADCs to my project using Processor Expert: ADC clock is below the 2.0MHz limit. 

 

I followed the default PE configuration and PE doesn't show any errors. The ADCs are mostly working correctly; I'm getting good readings if I measure against GND or VSS for both ADC channels with the exception that one channel seems to be loading the source more than the other. The slowest clock rate is selected (19.2 us).

 

I have Clock cfg 0 set to "Auto select" for both ADCs. It seems like PE is auto-selecting a clock configuration that isn't correct for the ADCs. Any idea why PE auto-selects a clock that the compiler complains about? 

 

*Edit: The channel loading issues were simply caused by external hardware on the FRDM board).

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