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JTAG board bring up

Question asked by Peter Paquette on Feb 22, 2017

Basic Info

  1. Custom board design based on NXP MCIMX6Q-Smart Device Board (Schematic # SPF-27516_C5)
  2. Kernel version and/or BSP release used
    1. MFGTool2 L4.1.15_2.0.0
    2. BSP - 2.1 Krogoth
    3. Uboot - v2016.07+gitAUTOINC+e6b42411ab-r0
    4. DDR_Stress_Tester_V1.0.3_UART1
    5. MX6Q_MMDC_LPDDR2_Register_Programming_Aid_V1.3.xlsx
  3. Any additional software/application or hardware used
    1. Segger JLink Pro using JLink V612i FW Rev 4.0 for gdb server
      1. JLinkGDBServerCL -device MCIMX6Q7 -speed 1000
      2. See jlink_gdbserver_log.txt
    2. MX6Q_MMDC_LPDDR2_Register_Programming_Aid_V1.3.xlsx
      1. Device Information  
        Memory type:LPDDR2
        Manufacturer:Micron - POP Package
        Memory part number:MT42L256M32D2LG-18 WTA
        Density per chip select (Gb):4
        Number of Chip Selects per channel used22
        Number of Channels used22
        DRAM density per channel (Gb)8
        Total DRAM density (Gb)16
        Number of ROW Addresses214
        Number of COLUMN Addresses210
        Number of BANKS28
        Bus Width (input 16, 32, or 64 bits)232
        Clock Cycle Freq (MHz)3533
        Clock Cycle Time (ns)1.876
    3. GNU Arm Embedded Toolchain 6-2016-q4-major (arm-non-eabi-gdb.exe) for gdb client
      1. arm-non-eabi-gdb -ix ddr-config.gdbinit
      2. See gdb_log.txt
  4. Hardware or software changes made from standard platform
    1. 2 x 1GB LPDDR2 Micron Ram (as shown above)
    2. No USB OTG port available (working on getting it red-wired out)
    3. JTAG - fully available and seems to be working (JMem works as well as JLink Commander)
    4. PMIC fully tested and working
    5. Hardware Development Guide for IMX6Q
      1. Followed all design checklist tables
      2. Followed ch8 board bring-up
        1. All power rails OK and stable + sequence
        2. All clocks checked
    6. Boot mode (01) - Serial downloader
    7. Debug UART1 (Serial -> USB) -> COM PORT 8 -> PUTTY running 115200, 8 data, 1 stop, No parity, No flow control
  5. Expected and observed behavior
    1. Read/write/verify to internal RAM 0x00907000 via JTAG OK
    2. Try to initialize DDR via gdbinit using programming aid outputs = FAILURE
      1. Load ddr-stress-test-mx6dq.elf
        1. Doesn't seem to run
        2. No output on serial UART
  6. Steps to reproduce (See above)
  7. Frequency of reproducibility = always
  8. Display type and resolution = N/A

 

 

 

A> Is there a way to simply test the Debug UART alone to see if it works?  - We are working on doing a boundary scan to make sure this and other pins are connected/not shorted.

B> Can we get a write up of logical steps or validation that this should work using JTAG only?

C> Is there a document/diagram that shows all the connections and signals needed for USB OTG needed to do serial download?

D> Anything else we can check?

E> Everything always references - check with your local FAE?  How do we get one?

Original Attachment has been moved to: ddr-config.gdbinit.zip

Original Attachment has been moved to: jlink_gdbserver_log.txt.zip

Original Attachment has been moved to: gdb_log.txt.zip

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