In the hardware design guidelines of IMX6Q it is mentioned that Add/CMD/CTL has to be length matched with clock signals. IMX6 DDR controller is having 2 clocks (Dram_sdclk0, Dram_sdclk1)each is given to two DDR's. We are facing a problem of length matching the clock's(Dram_sdclk0, Dram_sdclk1) to Address and command and control signals as we are routing ddr signal in fly by topology . So, we are using only one Dram_sdclk0 signal for all the four DDR's and terminating the second clock at the processor. Please suggest any changes required and recommendation about ddr address signal maximum possible length and about matching specific to fly by topology.