Hello Yuuki-San,
I’ve received the following information:
One delay value in this register is ~16.3 picoseconds. This is equivalent to tFS (Fine Step delay). This is a fixed value that does not vary with DDR clock frequency. The register field values of 0x00 - 0x08 add no delay. For this field, 0x08 is effectively the zero starting point. Every setting above 0x08 adds one tFS delay. For example, a value of 0x12 adds 10*tFS or 163 picoseconds of delay.
The register field will add a maximum of 32 delay elements. Therefore, the maximum setting of 0x28 will add 32*16.3 picoseconds delay, or 522 picoseconds. Any value above 0x28 adds no further delay, so 2 nanoseconds is not possible.
It is also not recommended to delay CKE by a full clock cycle (or 80%). The CKE signal is an integral part of the CA signals that go to the LPDDR2 memory. If the CKE signal is delayed by a clock cycle the LPDDR2 memory will decode the CA command incorrectly and the LPDDR2 will not operate. If the problem is that the CKE signal does not rise fast enough to meet tISCKE requirements is this issue what would need to be addressed.
The Reference Manual does report that CA[9:0] DeSkew should be set to 0x60 for low frequency operatons. CKE pads are different than other pads.
The CKE signal drive strength can be increased in field DRVDS_CON0.CACKEDRVRDS 0x3079009C[8:6]. Setting of 0x3 is maximum. If there is a pull down resistor on CKE, removing the resitor will also help.
I hope this information helps!
Regards,
