About the NVCC_DRAM_CKE Power supply for i.MX7

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About the NVCC_DRAM_CKE Power supply for i.MX7

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yuuki
Senior Contributor II

Dear all,

We want to cut down on power consumption at the time of the standby in the system.

We want to completely power off the i.MX7 and to enter DDR in Self Refresh mode.
The wake-up of i.MX7 is only POR.

In this case do we have only to supply power to NVCC_DRAM_CKE to keep a logic of CKE?
Can we power off the VDD_SNVS_IN?


We tried this constitution and see it to work well.
Does i.MX7 allow this operation?

NVCC_DRAM_CKE_for_i.MX7.jpg

Best  Regards,
Yuuki

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Yuuki,

You need to keep VDD_SNVS_IN alive in all low power modes otherwise the processor may have problems waking up or present unreliable behavior. As for the NVCC_DRAM_CKE you may keep it only if you wish to keep the DRAM in self-refresh mode, otherwise you may turn it off.

You mentioned that turning off VDD_SNVS_IN and keeping NCVV_DRAM_CKE worked okay for you (“waking” the processor with POR) however this configuration is not the intended use and you may encounter inconsistent behavior so I would strongly encourage against using it. For example you may lose the DRAM state.

I hope this information helps!

Regards,

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Yuuki,

You need to keep VDD_SNVS_IN alive in all low power modes otherwise the processor may have problems waking up or present unreliable behavior. As for the NVCC_DRAM_CKE you may keep it only if you wish to keep the DRAM in self-refresh mode, otherwise you may turn it off.

You mentioned that turning off VDD_SNVS_IN and keeping NCVV_DRAM_CKE worked okay for you (“waking” the processor with POR) however this configuration is not the intended use and you may encounter inconsistent behavior so I would strongly encourage against using it. For example you may lose the DRAM state.

I hope this information helps!

Regards,

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yuuki
Senior Contributor II

Dear gusarambula-san,

Thank you for your support.
We understood that it have a problem because DDRC and DDRP are reset by POR.

Best Regards,
Yuuki

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