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Question, i.MX6ULL power-up/down sequence

Question asked by AVNET JAPAN FAE (team share account) on Feb 19, 2017
Latest reply on Feb 20, 2017 by Yuri Muhin

Dear team,

 

I would like to ask about power-up/down sequence of i.MX6ULL.

Do you have any timing chart describing the power-up/down sequence of i.MX6ULL?

And my customer cannot find any description about the timing for NVCC_DRAM and NVCC_xxxx in i.MX6ULL datasheet.

Could you show me the power-up/down timing for NVCC_DRAM and NVCC_xxxx in addition to VDD_SNVS_IN and VDD_HIGH_IN?

 

Thanks,

Miyamoto

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