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Is it possible to reconfigure ACT_CSx and ADDRSx [10] in IOMUXC_GPR 1?

Question asked by Yasushi Hasegawa on Feb 19, 2017
Latest reply on Feb 19, 2017 by Yasushi Hasegawa

Dear Community,


Our customer is using i.MX 6Quad, so we refer to "i.MX 6 Dual / 6 Quad Applications Processor Reference Manual, Rev. 3, 07/2015".


They do Boot by Parallel NOR-FLASH.
The parallel NOR-FLASH is 128 Mbytes with the data bus being 16 bits and the address bus being 26bits [25: 0].
They wants to realize the following procedure.



[Requirements and Procedures]
When BOOT, download 128 Mbytes of data from parallel NOR-FLASH to DDR3 and execute on DDR3. In this case, EIM's CS0=128 MB, CS1=CS2=CS3= 0Byte.
At this time, CS0 is 128 Mbytes of parallel NOR-FLASH


After BOOT-download is finished, that is after [i] above, they want to use CS0= 64MBytes, CS1= 64MBytes, CS2=CS3= 0 Byte, and furthermore they want to reconfigure the setting of the EIM register for each CS0 and CS1.
At this time, the instruction is executed on DDR3. Also, CS0 and CS1 have been changed to another device instead of the parallel NOR-FLASH used in [i] above.



Is it possible to reconfigure the following registers when [ii] of [Requirements and Procedures] above?
- IOMUXC_GPR1 : Address 0x20E_0004h
   bit fields are ACT_CSx and ADDRSx [10]
- EIM registers


We have confirmed "22.4 Chip Select Memory Map" described on page 1013 of the Reference Manual.
If they wish to change Chip Select Memory Map when [ii] of [Requirements and Procedures] above, is it possible only by reconfiguring the following registers? Is there no other register or operation required?
- IOMUXC_GPR1 : Address 0x20E_0004h

   bit fields are ACT_CSx and ADDRSx [10]

Best Regards,
Yasushi Hasegawa