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BLE stack processor usage

Question asked by Michael Brudevold on Feb 16, 2017

I'm looking for any documentation that gives insight into the processor usage of the BLE stack running on a KW31Z.  In particular, I have some code that needs to disable interrupts in order to guarantee the timing on a bit-banged bus.  I don't necessarily need to have BLE active during this time, but if there's a means to schedule this code around the BLE library, I'd be interested.  Does any such documentation exist?


To give a little context, I'm used to BLE SoCs from Nordic or TI where the stack performs timing critical operations on the processor so you have to be careful to consider the needs of the stack.  However, my limited testing on this processor seems to indicate that timing critical operations are performed in the radio hardware such that I can pause the processor using the debugger and not lose the BLE connection.  So perhaps the answer is that there is no critical dependency and latency I introduce would only reduce the responsiveness but not prevent anything from working.