I am using the 8451 in the following configuration.
- ODR 800 Hz 4G scale
- I2C at 400kHz rate
- Sleep modes disabled. always in active mode
-FIFO in Circular Buffer mode.
-The only interrupt configured is "FIFO full" vectored to the Int1 pin. That is No watermarks or pulse/landscape/freefall detection enabled.
- On the interrupt I flush the FIFO 14 bit data...192 bytes.
- For speed of operation and hence current consumption I do not read either:
(a)The status register at 0x00. as I can guarantee I will service the interrupt and read out some data before the next sample is done 1.25mS later.
(b) The Interrupt source register at 0x0C as I only have one interrupt source.
This appears to works OK.
The interrupt on INT1 pin goes high approximately half way through the 5.2mS FIFO flush
However it is not clear from the datasheet that for correct operation you must read the interrupt source register to clear it.
Question: Must I clear the interrupt source register by reading it for correct operation
regards John Campbell